AIDAsoft Analog IC Design Automation


The AIDA framework implements an automatic analog IC design flow from a circuit-level specification to a physical layout description. The circuit-level synthesis is done by AIDA-C, and after the circuit-level design, AIDA-L takes the device sizes and the best floorplan, and generates the complete layout, which is then saved as a GDSII stream format.

AIDA-C is a circuit-level synthesizer supported by state-of-the-art multi-objective optimization kernels, where the robustness of the solutions is attained by considering user-defined worst case corners, that account for process variations and(or) PVT corners. The circuit's performance is measured using Spectre®, Eldo® or HSPICE® electrical circuit simulators.

Pareto optimal solution set for Area vs. DC Gain optimization with superimposed circuit layouts. AIDA-CL pareto front  

AIDA-L considers sized circuit to generate the complete layout by placing and, routing the devices, while fulfilling the technology design rules by using built-in DRC and LVS procedures. The router takes into account the circuit's currents to mitigate electromigration and IR-drop effects, and a fast but accurate PEX procedure provides parasitic estimates to be used in AIDA-C layout-aware optimization.

The framework's technology independent module generator, AIDA-AMG, is capable of creating several, simple and complex, device layout styles, allowing AIDA-C floorplan-aware sizing approach to explore a much wider space of solutions leading to higher quality layouts.

  Layout generated with AIDA-L  
Complete layout detailing the connections where EM effects caused wires width to increase.    
This work was supported in part by the Instituto de Telecomunicações (Research projects AIDA - IT/LA/1112/2011 and OPERA - PEst-OE/EEI/LA0008/2013) and by the Fundação para a Ciência e Tecnologia (Research project DISRUPTIVE EXCL/EEI-ELC/0261/2012, Grant FCT-DFRH-SFRH/BD/72698/ 2010, Grant FCT-SFRH/BD/86608/2012 and SFRH/BPD/104648/2014).
This work was also funded by FCT/MEC through national funds and when applicable co-funded by FEDER - PT2020 partnership agreement under the projects UID/EEA/50008/2019 and UIDB/50008/2020.
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