AIDAsoft Analog IC Design Automation

 

 

Publications

:: Journal Papers

  1. A. Gusmão, R. Vieira, N. Horta, N. Lourenço, and R. Martins, “Exploiting a Deep Learning Toolbox for Human-Machine Feedback towards Analog Integrated Circuit Placement Automation,” Electronics, vol. 11, no. 23, p. 3964, Nov. 2022. (doi: 10.3390/electronics11233964).

  2. A. Gusmão, N. Horta, N. Lourenço, and R. Martins, “Scalable and Order Invariant Analog Integrated Circuit Placement with Attention-based Graph-to-Sequence Deep Models,” Expert Systems with Applications, Elsevier, 2022.

  3. A. Gusmão, R. Póvoa, N. Horta, N. Lourenço, and R. Martins, “DeepPlacer: A Custom Integrated OpAmp Placement Tool using Deep Models,” Applied Soft Computing, Elsevier, vol. 115, 108188, Jan. 2022. (doi: 10.1016/ j.asoc.2021.108188)

  4. A. Canelas, F. Passos, N. Lourenço, R. Martins, E. Roca, R. Castro-López, N. Horta, and F. Fernández, “Hierarchical Yield-aware Synthesis Methodology Covering Device-, Circuit-, and System-level for Radiofrequency ICs,” IEEE Access, vol. 9, pp. 124152 – 124164, Sep. 2021. (doi: 10.1109/ACCESS.2021.3110758)

  5. L. Mendes, J. Vaz, F. Passos, N. Lourenço, and R. Martins, “In-depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications using One-and-Two-Step Design Optimization”, IEEE Access, vol. 9, pp. 70353 – 70368, May 2021. (doi: 10.1109/ACCESS.2021.3078240)

  6. E. Afacan, N. Lourenço, R. Martins, and G. Dündar, “Review: Machine Learning Techniques in Analog/RF Integrated Circuit Design, Synthesis, Layout, and Test,” Integration, the VLSI Journal, Elsevier, vol. 77, pp. 113-130, Mar. 2021. (doi: 10.1016/j.vlsi.2020.11.006)

  7. R. Martins, N. Lourenço, R. Póvoa, and N. Horta, “Shortening the Gap between Pre- and Post-Layout Analog IC Performance by Reducing the LDE-induced Variations with Multi-Objective Simulated Quantum Annealing,” Engineering Applications of Artificial Intelligence, vol. 98, 104102, Feb. 2021. (doi: 10.1016/j.engappai.2020.104102)

  8. R. Martins, N. Lourenço, N. Horta, S. Zhong, J. Yin, P.-I. Mak, and R. P. Martins, “Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3965-3977, Nov. 2020. (doi: 10.1109/TCSI.2020.3009857)

  9. F. Passos, E. Roca, R. Martins, N. Lourenço, S. Ahyoune, J. Sieiro, R. Castro-López, N. Horta, and F. Fernández, “Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology”, IEEE Access, vol. 8, pp. 51601–51609, Mar. 2020. (doi: 10.1109/ACCESS.2020.2980211)

  10. R. Póvoa, A. Canelas, R. Martins, N. Horta, N. Lourenço, and J. Goes, “A New Family of CMOS Inverter-Based OTAs for Biomedical and Healthcare Applications”, Integration, the VLSI Journal, Elsevier, vol. 71, pp. 38–48, Mar. 2020. (doi: 10.1016/j.vlsi.2019.12.004)

  11. R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, "A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications", IEEE Transactions on Circuits and Systems II: Express Briefs, 2019.

  12. R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, "Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow- Phase-Noise Cellular Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019.

  13. A. Canelas, R. P. Póvoa, R. M. Martins, N. Lourenço, J.G. Guilherme, J.P.C Carvalho, N. Horta, "FUZYE: A Fuzzy C-Means Analog IC Yield Optimization using Evolutionary-based Algorithms", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.

  14. R. Martins, N. Lourenço, F. Passos, R. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. Sieiro, F. V. Fernández, N. Horta "Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.

  15. F. Passos, R. Castro-López, E. Roca, F. Fernández, R. Martins, N. Lourenço, R. Póvoa, A. Canelas, N. Horta, "Enhanced Systematic Design of a Voltage Controlled Oscillator using a Two-Step Optimization Methodology," Integration, the VLSI, 2018.

  16. R. Póvoa, N. Lourenço, R. Martins, A. Canelas, N. Horta, and J. Goes, "Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current Starving," IEEE Transactions on Circuits and Systems II: Express Briefs, 2018.

  17. R. Póvoa, N. Lourenço, R. Martins, A. Canelas, N. Horta, and J. Goes, "Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement," IEEE Transactions on Circuits and Systems II: Express Briefs. 2017

  18. N. Lourenço, R. Martins, A. Canelas, R. Póvoa, and N. Horta, "AIDA: Robust Analog Circuit-Level Sizing and In-Loop Layout Generation", Integration, the VLSI Journal, 2016. DOI: 10.1016/j.vlsi.2016.04.009

  19. R. Martins, R. Póvoa, N. Lourenço, and N. Horta, "Current-flow & Current-Density-aware Multi-Objective Optimization of Analog IC Placement", Integration, the VLSI Journal, 2016. DOI: 10.1016/j.vlsi.2016.05.008

  20. R. Martins, N. Lourenço, A. Canelas, and N. Horta, "Stochastic-based Placement Template Generator for Analog IC Layout-Aware Synthesis," Integration, the VLSI Journal, 2017 (in press).

  21. R. Póvoa, I. Bastos, N. Lourenço, N. Horta, "Automatic Synthesis of RF Front-End Blocks Using Multi-Objective Evolutionary Techniques", Integration, the VLSI Journal, Elsevier, vol. 52, no. 1, pp. 243-252, 2016. (doi: 10.1016/j.vlsi.2015.04.005)

  22. R. Martins, N. Lourenço, and N. Horta, "Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates", Expert Systems with Applications, Elsevier, vol. 42, issue 23, pp. 9137-9151, Dec. 2015. (doi: 10.1016/j.eswa.2015.08.020)

  23. N. Lourenço, A. Canelas, R. Póvoa, R. Martins, N. Horta, "Floorplan-aware analog IC sizing and optimization based on topological constraints", Integration, the VLSI Journal, Elsevier, vol. 48, no. 1, pp.183-197, 2015 (doi: 10.1016/j.vlsi.2014.07.002).

  24. R. Martins, N. Lourenço, A. Canelas, N. Horta, "Electromigration-Aware Analog Router with Multilayer Multiport Terminal Structures", Integration, the VLSI Journal, Elsevier, vol. 47, no. 4, pp 532-547, 2014 (doi: 10.1016/j.vlsi.2014.02.003).

  25. R. Martins, N. Lourenço, N. Horta, "Routing Analog ICs using a Multi-Objective Multi-Constraint Evolutionary Approach", Analog Integrated Circuits and Signal Processing, Springer, vol. 78, no. 1, pp. 123-135, 2014 (doi: 10.1007/s10470-013-0088-9).

  26. R. Martins, N. Lourenço, N. Horta, "LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits", IEEE Transactions on Computer-Aided Design, vol. 32, no. 11, pp.1641-1654, 2013 (doi: 10.1109/TCAD.2013.2269050).

  27. M. Barros, J.Guilherme, N.C. Horta, "Analog Circuits Optimization based on Evolutionary Computation Techniques", Integration, the VLSI Journal, Elsevier, Vol. 43, No. 1, pp. 136 - 155, 2010 (doi: 10.1016/j.vlsi.2009.09.001).

    28. :: Conference Papers

  28. J. Domingues, A. Gusmão, N. Horta, N. Lourenço, R. Martins, “Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors,” in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Villasimius, Italy, June 2022.

  29. F. Passos, N. Lourenço, R. Martins, E. Roca, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, “Machine Learning Approaches for Transformer Modeling,” in International Conference on SMACD, Villasimius, Italy, June 2022.

  30. R. Vieira, F. Passos, R. P. Póvoa, R. Martins, N. Horta, J.G. Guilherme, N. Lourenço, “Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling,” in International Conference on SMACD, Villasimius, Italy, June 2022.

  31. P. Alves, A. Gusmão, N. Horta, N. Lourenço, R. Martins, “ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage,” in International Conference on SMACD, Villasimius, Italy, June 2022.

  32. N. Lourenço, F. Passos, R. Vieira, R. Martins, N. Horta, J.G. Guilherme, R. P. Póvoa, “Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/ºC Temperature Coefficient,” in International Conference on SMACD, Villasimius, Italy, June 2022.

  33. R. Vieira, F. Passos, A. Canelas, R. P. Póvoa, N. Lourenço, N. Horta, J.G. Guilherme, “A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/ºC Stability for Space Applications, IEEE International Symposium on Circuits and Systems (ISCAS), Austin, Texas, US, May 2022.

  34. L. Mendes, J. Vaz, F. Passos, N. Lourenço, and R. Martins, “Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS,” in IEEE ISCAS, Austin, USA, May 2022.

  35. P. Vaz, A. Gusmão, N. Horta, N. Lourenço, and R. Martins, “Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs,” in IEEE ISCAS, Austin, USA, May 2022.

  36. Gusmão, N. Horta, N. Lourenço, R. Martins, “Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, US, December 2021.

  37. R. Vieira, R. Martins, N. Horta, N. Lourenço, R. Póvoa, “A Sub-1µA Low-Power Low-Noise Amplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential Signals”, IEEE PhD. Research in Microelectronics and Electronics(PRIME), Erfurt, Germany, July 2021.

  38. R. Martins, A. Gusmão, A. Canelas, F. Passos, N. Lourenço, N. Horta, “An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization,” in International Conference on SMACD, Erfurt, Germany, July 2021.

  39. A. Gusmão, A. Canelas, N. Horta, N. Lourenço, R. Martins, A Deep Learning Toolbox for Analog Integrated Circuit Placement,” in International Conference on SMACD, Erfurt, Germany, July 2021.

  40. A. Gusmão, N. Lourenço, R. Martins, N. Horta, Bringing Structure into Analog IC Placement with Relational Graph Convolutional Networks,” in International Conference on SMACD, Erfurt, Germany, July 2021.

  41. J.G. Guilherme, R. Póvoa, N. Lourenço, N. Horta, “PROMISE, PROgrammable MIxed Signal ASIC Electronics Framework,” ESA International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications (AMICSA), Amsterdam, Netherlands, May 2021.

  42. A. Gusmão, F. Passos, R. Póvoa, N. Horta, N. Lourenço, R. Martins, “Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender,” IEEE ISCAS, Sevilla, Spain, October, 2020.

  43. N. Lourenço, E. Moutaye, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, " Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization" , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, July, 2019.

  44. N. Lourenço, E. Afacan, R. M. Martins, F. Passos, A. Canelas, R. P. Póvoa, N. Horta, G. Dundar, " Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing" , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, July, 2019.

  45. R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, JG Goes, " A LowNoise CMOS Inverter-Based OTA for Biomedical and Healthcare Signal Receivers" , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, July, 2019.

  46. D. Guerra, A. Canelas, R. P. Póvoa, N. Horta, N. Lourenço, R. M. Martins, " Artificial Neural Networks as an Alternative for Automatic Analog IC Placement" , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, July, 2019.

  47. R. M. Martins, N. Lourenço, R. P. Póvoa, N. Horta, " On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects" , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, July, 2019.

  48. R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, " Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm" , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, July, 2019.

  49. F. Passos, E. Roca, R. Castro-López and F. V. Fernández, R. Martins, N. Lourenço, R. Póvoa, A. Canelas and N. Horta, " Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs," in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, July 2018.

  50. N. Lourenço, J. Rosa, R. Martins, H. Aidos, R. Póvoa, A. Canelas and N. Horta, "On the Exploration of Promising Analog IC Designs via Artificial Neural Networks," in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, July 2018.

  51. A. Canelas, R. Póvoa, R. Martins, N. Lourenço and N. Horta, "A 20 dB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications," in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, July 2018.

  52. R. Martins, N. Lourenço, N. Horta, J. Yin, P. Mak and R. Martins, "Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications," in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, July 2018.

  53. R. Martins, N. Lourenço, N. Horta, J. Yin, P. Mak and R. Martins, "Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications," Work-in-Progress at Design Automation Conference, June 2018.

  54. T. Pessoa, N. Lourenço, R. Martins, R. Póvoa, and N. Horta, "Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel," in Design, Automation & Test in Europe Conference (DATE), March 2018.

  55. R. Póvoa, A. Canelas, R. Martins, N. Lourenço, Nuno Horta and João Goes, "A Dynamic Voltage-Combiners Biased OTA for Low-Power and High-Speed SC Circuits," in 11th Conference on PhD Research in Microelectronics and Electronics (PRIME), Taormina, Italy, June 2017.

  56. N. Lourenço, R. Martins, R. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca, F. Fernández, "New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing Optimization" in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Taormina, Italy, June 2017.

  57. F. Passos, R. Castro-López, E. Roca, F. Fernández, R. Martins, N. Lourenço, R. Póvoa, A. Canelas, N. Horta, "Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware Approach," in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Taormina, Italy, June 2017.

  58. R. Martins, N. Lourenço, R. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca, F. Fernández, "Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks," in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Taormina, Italy, June 2017.

  59. A. Canelas, R. Martins, R. Póvoa, N. Lourenço, and N. Horta, "Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisbon, Portugal, June 2016.

  60. R. Martins, A. Canelas, N. Lourenço, and N. Horta, "On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisbon, Portugal, June 2016. (Best Paper Award)

  61. A. Ferreira, N. Lourenço, R. Martins, and N. Horta, "Automated Analog IC Design Constraints Generation for a Layout-Aware Sizing Approach", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisbon, Portugal, June 2016.

  62. A. Canelas, R. Martins, R. Póvoa, N. Lourenço, and N. Horta, "Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC Sizing," Design, Automation & Test in Europe Conference (DATE), Lausanne, Switzerland, March 2017.

  63. D. Neves, R. Martins, N. Lourenço and N. Horta, "Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach", Design, Automation & Test in Europe Conference & Exhibition (DATE), March, 2016.

  64. R. Martins, N. Lourenço, N. Horta, N. Guerreiro, and M. Santos, "Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and Mixed-Signal Structural Testing", Conference on Design of Circuits and Integrated Systems (DCIS), Nov. 2015.

  65. D. Neves , N. Lourenço , N. Horta , "Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015.

  66. R. Martins, N. Lourenço, A. Canelas, R. Póvoa, and N. Horta, "AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015. (WINNER of the Design Automation Competition.).

  67. R. Martins, R. Póvoa, N. Lourenço, and N. Horta, "Exploring Design Tradeoffs in Analog IC Placement with Current-Flow & Current-Density Considerations", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015.

  68. B. Cardoso, R. Martins, N. Lourenço, and N. Horta, "AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing", 11th Conference on PhD Research in Microelectronics and Electronics (PRIME), June 2015.

  69. R. Martins, N. Lourenço, and N. Horta, "Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts", 11th Conference on PhD Research in Microelectronics and Electronics (PRIME), June 2015.

  70. R. Martins, N. Lourenço, A. Canelas, and N. Horta, "Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals", IEEE International Symposium on Circuits and Systems (ISCAS), May 2015.

  71. N. Lourenço, R. Martins, N. Horta, "Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction", Design, Automation & Test in Europe Conference & Exhibition (DATE), March, 2015.

  72. R. Póvoa, N. Lourenço, N. Horta, R. Santos-Tavares, J. Goes "A Cascode-Free Single-Stage Amplifier using a Fully-Differential Folded Voltage-Combiner", IEEE International Conf. on Electronics, Circuits and Systems (ICECS), Dec. 2014.

  73. R. Póvoa, R. Lourenço, N. Lourenço, A. Canelas, R. Martins, N. Horta, "LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques", IEEE International Symposium on Circuits and Systems, 2014 (ISCAS), June 2014. (Student Best Paper Award Runner-Up (2nd place)).

  74. R. Martins, N. Lourenço, A. Canelas, N. Horta, "Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures", Design, Automation & Test in Europe Conference & Exhibition (DATE), March. 2014

  75. R. Póvoa, N. Lourenço, N. Horta, R Santos-Tavares, J. Goes, "Single-Stage Amplifiers with Gain Enhancement and Improved Energy-Efficiency employing Voltage-Combiners", Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on, pp.19-22, Oct. 2013.

  76. F. Rocha, N. Lourenço, R. Póvoa, R. Martins, N. Horta, " A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis", Evolutionary Computation (CEC), 2013 IEEE Congress on, pp.2781-2788, June 2013.

  77. R. Martins, N. Lourenço, A. Canelas, N. Horta, "Multi-Port Multi-Terminal Analog Router based on an Evolutionary Optimization Kernel", Evolutionary Computation (CEC), 2013 IEEE Congress on, pp.2789-2796 June 2013.

  78. R. Martins, N. Lourenço, S. Rodrigues, J. Guilherme, N. Horta, "AIDA: Automated Analog IC Design Flow from Circuit Level to Layout", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on, pp.29-32, Sept. 2012. (Honorable Mention from SMACD 2012 Competition on Analog IC Design Automation).

  79. R. Martins, N. Lourenço, N. Horta, "Multi-Objective Multi-Constraint Routing of Analog ICs using a Modified NSGA-II Approach", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on, pp.65-68, Sept. 2012.

  80. N. Lourenço, N. Horta, "GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation", Proceedings of the Genetic and Evolutionary Computation Conference (GECCO-2012), pp.1119-1126, Jul. 2012.

  81. R. Martins, N. Lourenço, N. Horta, "LAYGEN II Automatic Analog ICs Layout Generator based on a Template Approach", Proceedings of the Genetic and Evolutionary Computation Conference (GECCO-2012), pp.1127-1134, Jul. 2012.

  82. P. Sousa, C. Duarte, N. Horta, "FUGA: A Fuzzy-Genetic Analog Circuit Optimization Kernel", Proceedings of the Genetic and Evolutionary Computation Conference (GECCO-2009), pp.1779-1780, Jul. 2009.

  83. P. Sousa. C. Duarte, M. Barros, J. Guilherme, N. Horta, "Enhancing Analog IC Design Optimization Kernels with Simple Fuzzy Models", Circuit Theory and Design, 2009. ECCTD 2009. European Conference on, pp.775-778, Aug. 2009.

  84. M. Barros, J. Guilherme, N. Horta, "An Evolutionary Optimization Kernel Using a Dynamic GA-SVM Model Applied to Analog IC Design", Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on , pp.32-35, Aug. 2007.

  85. M. Barros, J. Guilherme, N. Horta, "GA-SVM Feasibility Model and Optimization Kernel applied to Analog IC Design Automation", Proceedings of the 17th ACM Great Lakes symposium on VLSI (GLSVLSI '07), pp.469-472, Mar. 2007.

  86. M. Barros, J. Guilherme, N. Horta, "GA-SVM Optimization Kernel applied to Analog IC Design Automation", Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on , pp.486-489, Dec. 2006.

  87. G. Neves, M. Barros, N. Horta, "AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and Flow", Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on , pp.490-493, Dec. 2006.

  88. N. Lourenço, M. Vianello, J. Guilherme, N. Horta, "LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions", Research in Microelectronics and Electronics 2006, Ph. D. , vol., no., pp.213-216, Jun. 2006.

  89. N. Lourenço, N. Horta, "LAYGEN - An Evolutionary Approach to Automatic Analog IC Layout Generation", Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on , pp.1-4, Dec. 2005

  90. G. Neves, M. Barros, J. Guilherme, N. Horta, "A Design Automation Methodology for Analog IC Design Matching Designers Approach", Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on , vol.2, pp.549-552, July 2005.

  91. M. Barros, G. Neves, J.Guilherme, N. Horta, "An Evolutionary Optimization Kernel with Adaptive Parameters applied to Analog Circuit Design", Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on , vol.2, pp.545-548, July 2005.

  92. M. Barros, J. Silva, G. Neves, N. Horta, "Enhanced Genetic Algorithm Kernel Applied to a Circuit-Level Optimization E-Design Environment", Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on, vol.3, pp.1046-1049, Dec. 2003.

  93. J. Silva, N. Horta, "GENOM: Circuit-Level Optimizer Based on a Modified Genetic Algorithm Kernel", Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol.1, pp.745-748, May 2002.

    94. :: Books

  94. J. Domingues, P. Vaz, A. Gusmão, N. Horta, N. Lourenço, and R. Martins, “Speeding-Up Radio-Frequency Integrated Circuit Sizing with Neural Networks”, SpringerBriefs in Applied Sciences and Technology, Springer, 2023.

  95. R. Vieira, N. Horta, N. Lourenço, R. Póvoa, “Tunable Low-Power Low-Noise Amplifier for Healthcare Applications,” SpringerBriefs in Applied Sciences and Technology, Springer, 2021.ISBN 978-3-030-70887-0

  96. A. Gusmão, N. Horta, N. Lourenço, and R. Martins, “Analog IC Placement Generation via Neural Networks from Unlabeled Data,” SpringerBriefs in Applied Sciences and Technology, Springer, 2020. ISBN 978-3-030-50060-3

  97. J. Rosa, D. Guerra, N. Horta, R. Martins, N. Lourenço, “Using Artificial Neural Networks for Analog Integrated Circuit Design Automation”, Springer, 2020 ISBN: 978-3-030-35742-9

  98. Póvoa, R., Horta, n., Goes, J., "A New Family of Cascode-Free Amplifiers with High Energy-Efficiency and Gain Improvement," Springer, 2018. (doi:10.1007/978-3-319-95207-9)

  99. R. Martins, N. Lourenço, and N. Horta, "Analog Integrated Circuit Design Automation - Placement, Routing and Parasitic Extraction Techniques," Springer, 2017. Digital ISBN 978-3-319-34060-9; Hardcover ISBN 978-3-319-34059-3

  100. N. Lourenço, R. Martins, and N. Horta, "Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects," Springer, 2017. Digital ISBN 978-3-319-42037-0; Hardcover ISBN 978-3-319-42036-3

  101. R. Lourenço, N. Lourenço, N. Horta, "AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing" by Springer, SpringerBriefs, 2015 (ISBN 978-3-319-15954-6).

  102. F. Rocha, R. Martins, N. Lourenço, N. Horta, "Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms" by Springer, SpringerBriefs, 2014 (ISBN 978-3-319-02189-8).

  103. R. Martins, N. Lourenço, N. Horta, "Generating Analog IC Layout with LAYGEN II" by Springer, SpringerBriefs, 2013 (ISBN 978-3-642-33145-9).

  104. M. Barros, J. Guilherme, N. Horta, "Analog Circuits Optimization based on Evolutionary Computation Techniques" by Springer, Studies in Computational Intelligence, no. 294, 2010 (ISBN 978-3-642-12345-0).

    105. :: Book Chapters

  105. A. Canelas, R. Martins, R. Póvoa, N. Lourenço, J.G. Guilherme, N. Horta, "Enhancing an Automatic Analog IC Design Flow by using a Technology-Independent Module Generator", Chapter in Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI Global, 2014.

  106. R. Póvoa, R.Lourenço, N Lourenço, A. Canelas, R. Martins, N. Horta, "Synthesis of LC-Oscillators using Rival Multi-Objective/Multi-Constraint Optimization Kernels", Chapter in Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI Global, 2014.

  107. N. Lourenço, R. Martins, M. Barros, N. Horta, "Analog Circuit Design based on Robust POFs using an Enhanced MOEA with SVM Models" , Chapter in Analog/RF and Mixed-Signal Circuit Systematic Design, eds. Mourad Fakhfakh, Esteban Tlelo-Cuautle, Rafael Castro-Lopez, Springer, 2013.

 
This work was supported in part by the Instituto de Telecomunicações (Research projects AIDA - IT/LA/1112/2011 and OPERA - PEst-OE/EEI/LA0008/2013) and by the Fundação para a Ciência e Tecnologia (Research project DISRUPTIVE EXCL/EEI-ELC/0261/2012, Grant FCT-DFRH-SFRH/BD/72698/ 2010, Grant FCT-SFRH/BD/86608/2012 and SFRH/BPD/104648/2014).
This work was also funded by FCT/MEC through national funds and when applicable co-funded by FEDER - PT2020 partnership agreement under the projects UID/EEA/50008/2019 and UIDB/50008/2020.
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