AIDAsoft Analog IC Design Automation

Publications

:: Books

R. Lourenço, N. Lourenço, N. Horta, "AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing" by Springer, SpringerBriefs, 2015 (ISBN 978-3-319-15954-6).

F. Rocha, R. Martins, N. Lourenço, N. Horta, "Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms" by Springer, SpringerBriefs, 2014 (ISBN 978-3-319-02189-8).

R. Martins, N. Lourenço, N. Horta, "Generating Analog IC Layout with LAYGEN II" by Springer, SpringerBriefs, 2013 (ISBN 978-3-642-33145-9).

M. Barros, J. Guilherme, N. Horta, "Analog Circuits Optimization based on Evolutionary Computation Techniques" by Springer, Studies in Computational Intelligence, no. 294, 2010 (ISBN 978-3-642-12345-0).

:: Book Chapters

A. Canelas, R. Martins, R. Póvoa, N. Lourenço, J.G. Guilherme, N. Horta, "Enhancing an Automatic Analog IC Design Flow by using a Technology-Independent Module Generator", Chapter in Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI Global, 2014.

R. Póvoa, R.Lourenço, N Lourenço, A. Canelas, R. Martins, N. Horta, "Synthesis of LC-Oscillators using Rival Multi-Objective/Multi-Constraint Optimization Kernels", Chapter in Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI Global, 2014.

N. Lourenço, R. Martins, M. Barros, N. Horta, "Analog Circuit Design based on Robust POFs using an Enhanced MOEA with SVM Models" , Chapter in Analog/RF and Mixed-Signal Circuit Systematic Design, eds. Mourad Fakhfakh, Esteban Tlelo-Cuautle, Rafael Castro-Lopez, Springer, 2013.

:: Journal Papers

R. Póvoa, I. Bastos, N. Lourenço, N. Horta, "Automatic Synthesis of RF Front-End Blocks Using Multi-Objective Evolutionary Techniques", Integration, the VLSI Journal, Elsevier, vol. 52, no. 1, pp. 243-252, 2016. (doi: 10.1016/j.vlsi.2015.04.005)

R. Martins, N. Lourenço, and N. Horta, "Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates", Expert Systems with Applications, Elsevier, vol. 42, issue 23, pp. 9137-9151, Dec. 2015. (doi: 10.1016/j.eswa.2015.08.020)

N. Lourenço, A. Canelas, R. Póvoa, R. Martins, N. Horta, "Floorplan-aware analog IC sizing and optimization based on topological constraints", Integration, the VLSI Journal, Elsevier, vol. 48, no. 1, pp.183-197, 2015 (doi: 10.1016/j.vlsi.2014.07.002).

R. Martins, N. Lourenço, A. Canelas, N. Horta, "Electromigration-Aware Analog Router with Multilayer Multiport Terminal Structures", Integration, the VLSI Journal, Elsevier, vol. 47, no. 4, pp 532-547, 2014 (doi: 10.1016/j.vlsi.2014.02.003).

R. Martins, N. Lourenço, N. Horta, "Routing Analog ICs using a Multi-Objective Multi-Constraint Evolutionary Approach", Analog Integrated Circuits and Signal Processing, Springer, vol. 78, no. 1, pp. 123-135, 2014 (doi: 10.1007/s10470-013-0088-9).

R. Martins, N. Lourenço, N. Horta, "LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits", IEEE Transactions on Computer-Aided Design, vol. 32, no. 11, pp.1641-1654, 2013 (doi: 10.1109/TCAD.2013.2269050).

M. Barros, J.Guilherme, N.C. Horta, "Analog Circuits Optimization based on Evolutionary Computation Techniques", Integration, the VLSI Journal, Elsevier, Vol. 43, No. 1, pp. 136 - 155, 2010 (doi: 10.1016/j.vlsi.2009.09.001).

:: Conference Papers

D. Neves, R. Martins, N. Lourenço and N. Horta, "Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach", Design, Automation & Test in Europe Conference & Exhibition (DATE), March, 2016.

R. Martins, N. Lourenço, N. Horta, N. Guerreiro, and M. Santos, "Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and Mixed-Signal Structural Testing", Conference on Design of Circuits and Integrated Systems (DCIS), Nov. 2015.

D. Neves , N. Lourenço , N. Horta , "Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015.

R. Martins, N. Lourenço, A. Canelas, R. Póvoa, and N. Horta, "AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015. (WINNER of the Design Automation Competition.).

R. Martins, R. Póvoa, N. Lourenço, and N. Horta, "Exploring Design Tradeoffs in Analog IC Placement with Current-Flow & Current-Density Considerations", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015.

B. Cardoso, R. Martins, N. Lourenço, and N. Horta, "AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing", 11th Conference on PhD Research in Microelectronics and Electronics (PRIME), June 2015.

R. Martins, N. Lourenço, and N. Horta, "Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts", 11th Conference on PhD Research in Microelectronics and Electronics (PRIME), June 2015.

R. Martins, N. Lourenço, A. Canelas, and N. Horta, "Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals", IEEE International Symposium on Circuits and Systems (ISCAS), May 2015.

N. Lourenço, R. Martins, N. Horta, "Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction", Design, Automation & Test in Europe Conference & Exhibition (DATE), March, 2015.

R. Póvoa, N. Lourenço, N. Horta, R. Santos-Tavares, J. Goes "A Cascode-Free Single-Stage Amplifier using a Fully-Differential Folded Voltage-Combiner", IEEE International Conf. on Electronics, Circuits and Systems (ICECS), Dec. 2014.

R. Póvoa, R. Lourenço, N. Lourenço, A. Canelas, R. Martins, N. Horta, "LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques", IEEE International Symposium on Circuits and Systems, 2014 (ISCAS), June 2014. (Student Best Paper Award Runner-Up (2nd place)).

R. Martins, N. Lourenço, A. Canelas, N. Horta, "Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures", Design, Automation & Test in Europe Conference & Exhibition (DATE), March. 2014

R. Póvoa, N. Lourenço, N. Horta, R Santos-Tavares, J. Goes, "Single-Stage Amplifiers with Gain Enhancement and Improved Energy-Efficiency employing Voltage-Combiners", Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on, pp.19-22, Oct. 2013.

F. Rocha, N. Lourenço, R. Póvoa, R. Martins, N. Horta, " A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis", Evolutionary Computation (CEC), 2013 IEEE Congress on, pp.2781-2788, June 2013.

R. Martins, N. Lourenço, A. Canelas, N. Horta, "Multi-Port Multi-Terminal Analog Router based on an Evolutionary Optimization Kernel", Evolutionary Computation (CEC), 2013 IEEE Congress on, pp.2789-2796 June 2013.

R. Martins, N. Lourenço, S. Rodrigues, J. Guilherme, N. Horta, "AIDA: Automated Analog IC Design Flow from Circuit Level to Layout", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on, pp.29-32, Sept. 2012. (Honorable Mention from SMACD 2012 Competition on Analog IC Design Automation).

R. Martins, N. Lourenço, N. Horta, "Multi-Objective Multi-Constraint Routing of Analog ICs using a Modified NSGA-II Approach", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on, pp.65-68, Sept. 2012.

N. Lourenço, N. Horta, "GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation", Proceedings of the Genetic and Evolutionary Computation Conference (GECCO-2012), pp.1119-1126, Jul. 2012.

R. Martins, N. Lourenço, N. Horta, "LAYGEN II Automatic Analog ICs Layout Generator based on a Template Approach", Proceedings of the Genetic and Evolutionary Computation Conference (GECCO-2012), pp.1127-1134, Jul. 2012.

P. Sousa, C. Duarte, N. Horta, "FUGA: A Fuzzy-Genetic Analog Circuit Optimization Kernel", Proceedings of the Genetic and Evolutionary Computation Conference (GECCO-2009), pp.1779-1780, Jul. 2009.

P. Sousa. C. Duarte, M. Barros, J. Guilherme, N. Horta, "Enhancing Analog IC Design Optimization Kernels with Simple Fuzzy Models", Circuit Theory and Design, 2009. ECCTD 2009. European Conference on, pp.775-778, Aug. 2009.

M. Barros, J. Guilherme, N. Horta, "An Evolutionary Optimization Kernel Using a Dynamic GA-SVM Model Applied to Analog IC Design", Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on , pp.32-35, Aug. 2007.

M. Barros, J. Guilherme, N. Horta, "GA-SVM Feasibility Model and Optimization Kernel applied to Analog IC Design Automation", Proceedings of the 17th ACM Great Lakes symposium on VLSI (GLSVLSI '07), pp.469-472, Mar. 2007.

M. Barros, J. Guilherme, N. Horta, "GA-SVM Optimization Kernel applied to Analog IC Design Automation", Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on , pp.486-489, Dec. 2006.

G. Neves, M. Barros, N. Horta, "AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and Flow", Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on , pp.490-493, Dec. 2006.

N. Lourenço, M. Vianello, J. Guilherme, N. Horta, "LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions", Research in Microelectronics and Electronics 2006, Ph. D. , vol., no., pp.213-216, Jun. 2006.

N. Lourenço, N. Horta, "LAYGEN - An Evolutionary Approach to Automatic Analog IC Layout Generation", Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on , pp.1-4, Dec. 2005

G. Neves, M. Barros, J. Guilherme, N. Horta, "A Design Automation Methodology for Analog IC Design Matching Designers Approach", Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on , vol.2, pp.549-552, July 2005.

M. Barros, G. Neves, J.Guilherme, N. Horta, "An Evolutionary Optimization Kernel with Adaptive Parameters applied to Analog Circuit Design", Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on , vol.2, pp.545-548, July 2005.

M. Barros, J. Silva, G. Neves, N. Horta, "Enhanced Genetic Algorithm Kernel Applied to a Circuit-Level Optimization E-Design Environment", Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on, vol.3, pp.1046-1049, Dec. 2003.

J. Silva, N. Horta, "GENOM: Circuit-Level Optimizer Based on a Modified Genetic Algorithm Kernel", Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol.1, pp.745-748, May 2002.

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