
Publications
:: Books
R. Martins, N. Lourenço, and N. Horta, "Analog Integrated Circuit Design Automation  Placement, Routing and Parasitic Extraction Techniques," Springer, 2017. Digital ISBN 9783319340609; Hardcover ISBN 9783319340593
N. Lourenço, R. Martins, and N. Horta, "Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects," Springer, 2017. Digital ISBN 9783319420370; Hardcover ISBN 9783319420363
R. Lourenço, N. Lourenço, N. Horta,
"AIDACMK: MultiAlgorithm Optimization Kernel Applied to Analog IC Sizing"
by Springer, SpringerBriefs, 2015 (ISBN 9783319159546).
F. Rocha, R. Martins, N. Lourenço, N. Horta,
"Electronic Design Automation of Analog ICs combining Gradient Models with MultiObjective Evolutionary Algorithms"
by Springer, SpringerBriefs, 2014 (ISBN 9783319021898).
R. Martins, N. Lourenço, N. Horta,
"Generating Analog IC Layout with LAYGEN II"
by Springer, SpringerBriefs, 2013 (ISBN 9783642331459).
M. Barros, J. Guilherme, N. Horta,
"Analog Circuits Optimization based on Evolutionary Computation Techniques"
by Springer, Studies in Computational Intelligence, no. 294, 2010 (ISBN 9783642123450).
:: Book Chapters
A. Canelas, R. Martins, R. Póvoa, N. Lourenço, J.G. Guilherme, N. Horta,
"Enhancing an Automatic Analog IC Design Flow by using a TechnologyIndependent Module Generator",
Chapter in Performance Optimization Techniques in Analog, MixedSignal, and RadioFrequency Circuit Design, Mourad Fakhfakh, Esteban TleloCuautle, Maria Helena Fino, IGI Global, 2014.
R. Póvoa, R.Lourenço, N Lourenço, A. Canelas, R. Martins, N. Horta,
"Synthesis of LCOscillators using Rival MultiObjective/MultiConstraint Optimization Kernels",
Chapter in Performance Optimization Techniques in Analog, MixedSignal, and RadioFrequency Circuit Design, Mourad Fakhfakh, Esteban TleloCuautle, Maria Helena Fino, IGI Global, 2014.
N. Lourenço, R. Martins, M. Barros, N. Horta,
"Analog Circuit Design based on Robust POFs using an Enhanced MOEA with SVM Models" ,
Chapter in Analog/RF and MixedSignal Circuit Systematic Design, eds. Mourad Fakhfakh, Esteban TleloCuautle, Rafael CastroLopez, Springer, 2013.
:: Journal Papers
R. Póvoa, N. Lourenço, R. Martins, A. Canelas, N. Horta, and J. Goes, "SingleStage Amplifier biased by VoltageCombiners with Gain and EnergyEfficiency Enhancement," IEEE Transactions on Circuits and Systems II: Express Briefs.
N. Lourenço, R. Martins, A. Canelas, R. Póvoa, and N. Horta, "AIDA: Robust Analog CircuitLevel Sizing and InLoop Layout Generation", Integration, the VLSI Journal, 2016. DOI: 10.1016/j.vlsi.2016.04.009
R. Martins, R. Póvoa, N. Lourenço, and N. Horta, "Currentflow & CurrentDensityaware MultiObjective Optimization of Analog IC Placement", Integration, the VLSI Journal, 2016. DOI: 10.1016/j.vlsi.2016.05.008
R. Martins, N. Lourenço, A. Canelas, and N. Horta, "Stochasticbased Placement Template Generator for Analog IC LayoutAware Synthesis," Integration, the VLSI Journal, 2017 (in press).
R. Póvoa, I. Bastos, N. Lourenço, N. Horta,
"Automatic Synthesis of RF FrontEnd Blocks Using MultiObjective Evolutionary Techniques",
Integration, the VLSI Journal, Elsevier, vol. 52, no. 1, pp. 243252, 2016. (doi: 10.1016/j.vlsi.2015.04.005)
R. Martins, N. Lourenço, and N. Horta,
"Multiobjective optimization of analog integrated circuit placement hierarchy in absolute coordinates",
Expert Systems with Applications, Elsevier, vol. 42, issue 23, pp. 91379151, Dec. 2015. (doi: 10.1016/j.eswa.2015.08.020)
N. Lourenço, A. Canelas, R. Póvoa, R. Martins, N. Horta,
"Floorplanaware analog IC sizing and optimization based on topological constraints",
Integration, the VLSI Journal, Elsevier, vol. 48, no. 1, pp.183197, 2015 (doi: 10.1016/j.vlsi.2014.07.002).
R. Martins, N. Lourenço, A. Canelas, N. Horta,
"ElectromigrationAware Analog Router with Multilayer Multiport Terminal Structures",
Integration, the VLSI Journal, Elsevier, vol. 47, no. 4, pp 532547, 2014 (doi: 10.1016/j.vlsi.2014.02.003).
R. Martins, N. Lourenço, N. Horta,
"Routing Analog ICs using a MultiObjective MultiConstraint Evolutionary Approach",
Analog Integrated Circuits and Signal Processing, Springer, vol. 78, no. 1, pp. 123135, 2014 (doi: 10.1007/s1047001300889).
R. Martins, N. Lourenço, N. Horta,
"LAYGEN II  Automatic Layout Generation of Analog Integrated Circuits",
IEEE Transactions on ComputerAided Design, vol. 32, no. 11, pp.16411654, 2013 (doi: 10.1109/TCAD.2013.2269050).
M. Barros, J.Guilherme, N.C. Horta,
"Analog Circuits Optimization based on Evolutionary Computation Techniques",
Integration, the VLSI Journal, Elsevier, Vol. 43, No. 1, pp. 136  155, 2010 (doi: 10.1016/j.vlsi.2009.09.001).
:: Conference Papers
A. Canelas, R. Martins, R. Póvoa, N. Lourenço, and N. Horta, "Yield Optimization using KMeans Clustering Algorithm to reduce Monte Carlo Simulations", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisbon, Portugal, June 2016.
R. Martins, A. Canelas, N. Lourenço, and N. Horta, "Onthefly Exploration of Placement Templates for Analog IC Layoutaware Sizing Methodologies", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisbon, Portugal, June 2016. (Best Paper Award)
A. Ferreira, N. Lourenço, R. Martins, and N. Horta, "Automated Analog IC Design Constraints Generation for a LayoutAware Sizing Approach", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisbon, Portugal, June 2016.
A. Canelas, R. Martins, R. Póvoa, N. Lourenço, and N. Horta, "Efficient Yield Optimization Method using a Variable KMeans Algorithm for Analog IC Sizing," Design, Automation & Test in Europe Conference (DATE), Lausanne, Switzerland, March 2017.
D. Neves, R. Martins, N. Lourenço and N. Horta,
"Design Automation Tasks Scheduling for Enhanced Parallel Execution of a StateoftheArt LayoutAware Sizing Approach",
Design, Automation & Test in Europe Conference & Exhibition (DATE), March, 2016.
R. Martins, N. Lourenço, N. Horta, N. Guerreiro, and M. Santos,
"Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and MixedSignal Structural Testing",
Conference on Design of Circuits and Integrated Systems (DCIS), Nov. 2015.
D. Neves , N. Lourenço , N. Horta ,
"Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis",
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015.
R. Martins, N. Lourenço, A. Canelas, R. Póvoa, and N. Horta,
"AIDA: Robust LayoutAware Synthesis of Analog ICs including Sizing and Layout",
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015.
(WINNER of the Design Automation Competition.).
R. Martins, R. Póvoa, N. Lourenço, and N. Horta,
"Exploring Design Tradeoffs in Analog IC Placement with CurrentFlow & CurrentDensity Considerations",
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Sept. 2015.
B. Cardoso, R. Martins, N. Lourenço, and N. Horta,
"AIDAPEx: Accurate Parasitic Extraction for LayoutAware Analog Integrated Circuit Sizing",
11th Conference on PhD Research in Microelectronics and Electronics (PRIME), June 2015.
R. Martins, N. Lourenço, and N. Horta,
"Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts",
11th Conference on PhD Research in Microelectronics and Electronics (PRIME), June 2015.
R. Martins, N. Lourenço, A. Canelas, and N. Horta,
"Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals",
IEEE International Symposium on Circuits and Systems (ISCAS), May 2015.
N. Lourenço, R. Martins, N. Horta,
"LayoutAware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction",
Design, Automation & Test in Europe Conference & Exhibition (DATE), March, 2015.
R. Póvoa, N. Lourenço, N. Horta, R. SantosTavares, J. Goes
"A CascodeFree SingleStage Amplifier using a FullyDifferential Folded VoltageCombiner",
IEEE International Conf. on Electronics, Circuits and Systems (ICECS), Dec. 2014.
R. Póvoa, R. Lourenço, N. Lourenço, A. Canelas, R. Martins, N. Horta,
"LCVCO Automatic Synthesis Using MultiObjective Evolutionary Techniques",
IEEE International Symposium on Circuits and Systems, 2014 (ISCAS), June 2014.
(Student Best Paper Award RunnerUp (2nd place)).
R. Martins, N. Lourenço, A. Canelas, N. Horta,
"ElectromigrationAware and IRDrop Avoidance Routing in Analog Multiport Terminal Structures",
Design, Automation & Test in Europe Conference & Exhibition (DATE), March. 2014
R. Póvoa, N. Lourenço, N. Horta, R SantosTavares, J. Goes,
"SingleStage Amplifiers with Gain Enhancement and Improved EnergyEfficiency employing VoltageCombiners",
Very Large Scale Integration (VLSISoC), 2013 IFIP/IEEE 21st International Conference on, pp.1922, Oct. 2013.
F. Rocha, N. Lourenço, R. Póvoa, R. Martins, N. Horta, "
A New Metaheuristc Combining Gradient Models with NSGAII to Enhance Analog IC Synthesis",
Evolutionary Computation (CEC), 2013 IEEE Congress on, pp.27812788, June 2013.
R. Martins, N. Lourenço, A. Canelas, N. Horta,
"MultiPort MultiTerminal Analog Router based on an Evolutionary Optimization Kernel",
Evolutionary Computation (CEC), 2013 IEEE Congress on, pp.27892796 June 2013.
R. Martins, N. Lourenço, S. Rodrigues, J. Guilherme, N. Horta,
"AIDA: Automated Analog IC Design Flow from Circuit Level to Layout",
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on, pp.2932, Sept. 2012.
(Honorable Mention from SMACD 2012 Competition on Analog IC Design Automation).
R. Martins, N. Lourenço, N. Horta,
"MultiObjective MultiConstraint Routing of Analog ICs using a Modified NSGAII Approach",
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on, pp.6568, Sept. 2012.
N. Lourenço, N. Horta,
"GENOMPOF: MultiObjective Evolutionary Synthesis of Analog ICs with Corners Validation",
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO2012), pp.11191126, Jul. 2012.
R. Martins, N. Lourenço, N. Horta,
"LAYGEN II Automatic Analog ICs Layout Generator based on a Template Approach",
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO2012), pp.11271134, Jul. 2012.
P. Sousa, C. Duarte, N. Horta,
"FUGA: A FuzzyGenetic Analog Circuit Optimization Kernel",
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO2009), pp.17791780, Jul. 2009.
P. Sousa. C. Duarte, M. Barros, J. Guilherme, N. Horta,
"Enhancing Analog IC Design Optimization Kernels with Simple Fuzzy Models",
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on, pp.775778, Aug. 2009.
M. Barros, J. Guilherme, N. Horta,
"An Evolutionary Optimization Kernel Using a Dynamic GASVM Model Applied to Analog IC Design",
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on , pp.3235, Aug. 2007.
M. Barros, J. Guilherme, N. Horta,
"GASVM Feasibility Model and Optimization Kernel applied to Analog IC Design Automation",
Proceedings of the 17th ACM Great Lakes symposium on VLSI (GLSVLSI '07), pp.469472, Mar. 2007.
M. Barros, J. Guilherme, N. Horta,
"GASVM Optimization Kernel applied to Analog IC Design Automation",
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on , pp.486489, Dec. 2006.
G. Neves, M. Barros, N. Horta,
"AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and Flow",
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on , pp.490493, Dec. 2006.
N. Lourenço, M. Vianello, J. Guilherme, N. Horta,
"LAYGEN  Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions",
Research in Microelectronics and Electronics 2006, Ph. D. , vol., no., pp.213216, Jun. 2006.
N. Lourenço, N. Horta,
"LAYGEN  An Evolutionary Approach to Automatic Analog IC Layout Generation",
Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on , pp.14, Dec. 2005
G. Neves, M. Barros, J. Guilherme, N. Horta,
"A Design Automation Methodology for Analog IC Design Matching Designers Approach",
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on , vol.2, pp.549552, July 2005.
M. Barros, G. Neves, J.Guilherme, N. Horta,
"An Evolutionary Optimization Kernel with Adaptive Parameters applied to Analog Circuit Design",
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on , vol.2, pp.545548, July 2005.
M. Barros, J. Silva, G. Neves, N. Horta,
"Enhanced Genetic Algorithm Kernel Applied to a CircuitLevel Optimization EDesign Environment",
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on, vol.3, pp.10461049, Dec. 2003.
J. Silva, N. Horta,
"GENOM: CircuitLevel Optimizer Based on a Modified Genetic Algorithm Kernel",
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol.1, pp.745748, May 2002.
